As semiconductor devices, such as memory devices, are becoming increasingly integrated, achieved degree of integration with typical two-dimensional (2D) structures is rapidly approaching its limit. Therefore, there is a need for a semiconductor memory device having a three-dimensional (3D) structure that exceeds the 2D structure in integration capability. Such need has led to extensive research into developing 3D semiconductor memory device technology.
In a 3D semiconductor memory device, various signals carrying data, commands, or addresses are transmitted, some or all of which are transmitted through a through silicon via (TSV). However, a large thermal expansion mismatch exists between the substrate and metal filler (such as copper), resulting in substrate stress and warpage, which strongly impact TSV performance and reliability.
This Discussion of the Background section is provided for background information only. The statements in this Discussion of the Background are not an admission that the subject matter disclosed in this Discussion of the Background section constitutes prior art to the present disclosure, and no part of this Discussion of the Background section may be used as an admission that any part of this application, including this Discussion of the Background section, constitutes prior art to the present disclosure.